This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on\nFPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction\nthan, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable\nof achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early systemlevel\ndesign space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework.\nSubsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of\nMicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.
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